High Performance Computing Nodes Using a DEC Alpha Processor and a T9000 Transputer
Paper: 399
Session: B (poster)
Presenter: Heeley, Roger, CERN, Geneva
Keywords: data acquisition systems, switches (eg ATM, trigger systems
High Performance Computing Nodes Using a DEC Alpha Processor and a T9000
Transputer
Author name(s) come here
Institutional affiliation should be put here, together with address
This field is for the Collaboration name (if needed)
P. D. Maley
The University of Liverpool, Liverpool, England
R.W. Dobinson, R. Heeley
CERN, Geneva, Switzerland
Abstract
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(300-500 words summary which highlights
the scope and significance of the paper,
including a statement of the current status of the work).
The T9000 Transputer has been used successfully in the CPLEAR experiment at
CERN to perform on-line event reconstruction. Its computational performance
was found to be poor compared to the latest generation of microprocessors.
However, when integrated into networks using STC104 packet switches, it
achieves a scalable communications performance which compares favourable with
current distributed memory computers.
Modern state of the art microprocessors offer high computational performance,
several hundred MIPS or MFLOPS, using high clock speeds and pipelined
superscaler architectures, but lack scalable multiprocessor communications
capabilities.
A high performance computing node has been designed and constructed using a
T9000 Transputer as a communications controller for a DEC Alpha 21066A
microprocessor. Such a hybrid node combines the two complementary strengths of
the two processors into a so called TransAlpha module.
The event reconstruction program used by the CPLEAR experiment has been ported
to the TransAlpha and successfully run on a small network. Its real time
performance and reliability have been demonstrated.
The approach adopted by the TransAlpha modules is being further investigated
within the framework of the ATLAS experiment.